Tenstorrent is seeking a skilled Design Verification Engineer to join their RISC-V CPU team in Bengaluru, India. The role involves developing verification environments and ensuring the quality of next-generation IP solutions, with a focus on collaboration and problem-solving
Job Summary
You will be responsible for the block-level verification of high-performance Cache and Coherence units, leading the development of sophisticated UVM environments.
Define comprehensive verification strategies and architect robust DV environments for block and sub-system level IPs, developing reusable UVCs and executing constrained-random test plans.
You will gain deep hands-on exposure to cache pipelines, memory subsystems, high-performance interconnects, and advanced verification techniques.
Matching Summary
Match Score: 85
Tenstorrent is seeking a skilled Design Verification Engineer to join their RISC-V CPU team in Bengaluru, India. The role involves developing verification environments and ensuring the quality of next-generation IP solutions, with a focus on collaboration and problem-solving.
Skills & Requirements
Must-have
SystemVerilog and UVM
build verification environments
RTL verification, debugging, coverage
cache, interconnects, or memory systems
Nice-to-have
independent complex DV efforts
problem-solving skills
collaboration and curiosity
Key Requirements
Eligibility to access U.S. export-controlled technology
Citizenship/permanent residency status or ability to obtain prior license approval
Work Rights
Eligibility to access U.S. export-controlled technology