Senior Hardware Asic Arch/design Engineer

NXP Semiconductors

Hyderabad, India
Ai inference workloads
Hardware-software co-design
Asic architecture and micro-architecture
Define product feature and capabilities and own the architecture for compute, memory, interconnect & high-speed interface subsystems in the AI inference chip

Job Summary

  • Define product feature and capabilities and own the architecture for compute, memory, interconnect & high-speed interface subsystems in the AI inference chip.
  • Collaborate with various software teams to co-optimize hardware features for AI workloads.
  • Develop and maintain high-level architecture and performance models.

Matching Summary

Define product feature and capabilities and own the architecture for compute, memory, interconnect & high-speed interface subsystems in the AI inference chip.

Skills & Requirements

Must-have

  • AI inference workloads
  • hardware-software co-design
  • ASIC architecture and micro-architecture
  • high-speed interface subsystems
  • PPA analysis and trade-off

Nice-to-have

  • edge deployments
  • long-term software scalability
  • debuggability features

Key Requirements

  • Senior Hardware ASIC Arch/design Engineer

Work Rights

Not specified

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