Sr. Soc Design Verification Engineer

Altera

Bengaluru, Karnataka, India
10+ years experience with complex asic designs
System verilog language proficiency
Uvm verification methodology expertise

Skills & Requirements

Must-have

  • 10+ years experience with complex ASIC designs
  • System Verilog language proficiency
  • UVM verification methodology expertise
  • Linux/Unix scripting skills
  • Design for Debug architecture knowledge

Nice-to-have

  • Emulation experience
  • ARM and RISC Debug Architectures familiarity
  • UltraSoC or Tessent Embedded Analytics background
  • Cross-functional team collaboration
  • Global site coordination ability

Key Requirements

  • 10+ years of experience with complex ASIC designs
  • Proficiency in System Verilog and UVM
  • Working knowledge of Perl or Python scripting

Work Rights

Not specified

Tailored Resume

Cover Letter