Principal Silicon Physical Design And Layout Engineer - Terawave
Blue Origin
Multiple Locations, US
Ca applicants is $230,773.00 - $323,081.85; wa app...
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Physical design and layout of asics
Analog and digital processing integration
Floor planning and power distribution
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Blue Origin is seeking a Principal Silicon Physical Design and Layout Engineer to develop advanced integrated circuits for its TeraWave satellite communications network. The ideal candidate will possess extensive experience in physical design and layout of ASICs, with a focus on both analog and digital processing in a fast-paced, innovative environment.
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Job Summary
Execute physical design and layout of ASICs that integrate both analog and digital processing for satellite communication systems.
Implement floor planning, power distribution, clock tree synthesis, and routing for complex mixed-signal designs.
Optimize layouts for radiation tolerance and reliability in the space environment.
Matching Summary
Match Score: 75
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Blue Origin is seeking a Principal Silicon Physical Design and Layout Engineer to develop advanced integrated circuits for its TeraWave satellite communications network. The ideal candidate will possess extensive experience in physical design and layout of ASICs, with a focus on both analog and digital processing in a fast-paced, innovative environment.
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Salary
CA applicants is $230,773.00 - $323,081.85; WA applicants is $230,773.00 - $323,081.85; Other site ranges may differ
Skills & Requirements
Must-have
Physical design and layout of ASICs
Analog and digital processing integration
Floor planning and power distribution
Clock tree synthesis and routing
Timing closure and signal integrity
Physical verification (DRC/LVS/ERC)
RF processing technologies
Radiation tolerance optimization
Nice-to-have
Fast-paced innovation environment
Mission-critical execution
Collaboration with front-end designers
Data analytics for performance optimization
Manufacturability and yield optimization
Design for test (DFT) implementation
Key Requirements
B.S. degree in Electrical Engineering or related field
10+ years of experience in ASIC physical design
Digital and analog layout techniques expertise
Experience with EDA tools (Cadence, Synopsys, Mentor)
Knowledge of semiconductor fabrication processes
Understanding of timing closure and signal integrity
Experience with power analysis and optimization
Work Rights
Must be a US citizen or national, permanent resident, or lawfully admitted