Asic Design Verfication Engineer Ii (full Time) - United States

Cisco UK

United States
New york city metro area: $123,600 - $200,100; non...
**
Verilog or vhdl hardware description languages
Rtl design and simulation tools experience
Python, perl, or tcl scripting exposure
** Cisco is seeking an ASIC Design Verification Engineer II to join their team, focusing on digital hardware development and verification. The role involves collaboration across various departments to design and deliver innovative products that impact global communication networks. **

Job Summary

  • Join an award-winning ASIC team to collaborate with top industry talent on designing ground-breaking communications and network processing silicon.
  • Contribute to system architecture, high-speed logic design, and verification while owning projects from concept to in-house physical implementation.
  • Enjoy comprehensive benefits including medical, dental, vision insurance, a 401(k) match, paid parental leave, and flexible vacation time.

Matching Summary

Match Score: 75

** Cisco is seeking an ASIC Design Verification Engineer II to join their team, focusing on digital hardware development and verification. The role involves collaboration across various departments to design and deliver innovative products that impact global communication networks. **

Salary

New York City Metro Area: $123,600 - $200,100; Non-Metro NY/Washington: $109,900 - $181,600; Bonus/Equity: Eligible for annual bonuses and restricted stock units

Skills & Requirements

Must-have

  • Verilog or VHDL hardware description languages
  • RTL design and simulation tools experience
  • Python, Perl, or TCL scripting exposure

Nice-to-have

  • UVM and SystemVerilog verification methodologies
  • Linux-based development environment familiarity
  • Adaptability to new technologies and problem-solving

Key Requirements

  • Bachelor's degree plus 2 years experience OR Master's degree
  • Completion within past 3 years or current enrollment expected within 12 months
  • Familiarity with ASIC/SoC design flow including synthesis and timing closure

Work Rights

Not specified

Tailored Resume

Cover Letter