Principal Asic Design Engineer

ON Semiconductor

Bangalore, Karnataka, India
7+ years semiconductor product development experience
Rtl coding in verilog/systemverilog
Soc architecture and ip selection expertise
This role involves leading a Sub-System for the innovative Treo Platform which supports voltage ranges from 1–90V and operates up to 175°C

Job Summary

  • This role involves leading a Sub-System for the innovative Treo Platform which supports voltage ranges from 1–90V and operates up to 175°C.
  • The successful candidate will be responsible for micro-architecting, implementing, and verifying digital Sub-Systems while ensuring they meet ASIL requirements.
  • onsemi offers a diverse set of world-class products in a friendly atmosphere with opportunities for continual learning and international project participation.

Matching Summary

This role involves leading a Sub-System for the innovative Treo Platform which supports voltage ranges from 1–90V and operates up to 175°C.

Skills & Requirements

Must-have

  • 7+ years semiconductor product development experience
  • RTL coding in Verilog/SystemVerilog
  • SoC architecture and IP selection expertise
  • Digital design principles FSM timing analysis
  • Experience with APB AHB AXI SPI I2C interfaces
  • Knowledge of ASIL functional safety requirements

Nice-to-have

  • Experience with AI-driven digital design tools
  • Exposure to platform standardization strategies
  • Proficiency in Python and PERL scripting
  • Familiarity with Lint CDC RDC tools
  • Ability to lead small projects effectively

Key Requirements

  • BE/ME in electronics or related technical field
  • At least 7 years of relevant experience in semiconductor product development
  • Strong grasp of digital design principles and verification techniques

Work Rights

Not specified

Tailored Resume

Cover Letter