Senior Serdes And Memory Ip Ae Group Director

Cadence

Base: $187,600 to $348,400 (california); bonus/equ...
Fully remote
20+ years of relevant experience
Msee or phd degree required
High-speed interface phy and controller ip expertise
The role involves leading a team of senior application engineers focused on technical presales for high-speed interface PHYs and controllers

Job Summary

  • The role involves leading a team of senior application engineers focused on technical presales for high-speed interface PHYs and controllers.
  • Candidates will develop strategies to secure complex bundle IP deals encompassing memory, Serdes, and foundation IPs while leveraging AI for efficiency.
  • The position offers competitive compensation including an On Target Earnings structure with bonus, equity, and comprehensive benefits like 401(k) matching.

Matching Summary

The role involves leading a team of senior application engineers focused on technical presales for high-speed interface PHYs and controllers.

Salary

Base: $187,600 to $348,400 (California); Bonus/Equity: Eligible for incentive compensation; Benefits: Paid vacation, 401(k) match, medical/dental/vision

Skills & Requirements

Must-have

  • 20+ years of relevant experience
  • MSEE or PhD degree required
  • High-speed interface PHY and controller IP expertise
  • SoC architecture and system-level design knowledge
  • Experience with DDR, LPDDR, HBM, PCIe, CXL protocols
  • Leadership of highly technical engineering teams

Nice-to-have

  • Strong interpersonal and communication skills
  • Familiarity with AI, Cloud, Networking market segments
  • Exposure to analog/mixed-signal design flows
  • Willingness to travel approximately 10% of the time
  • Ability to influence product roadmap via customer feedback

Key Requirements

  • MSEE with 20+ years experience or PhD with 15+ years
  • Management experience leading technical teams
  • Prior IP or SoC design experience
  • Knowledge of JEDEC and PCI-SIG standards

Work Rights

Not specified

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