Physical Design Timing Engineer

Intel Corporation

Bangalore, India
Timing analysis and optimization
Timing constraint generation and verification
Soc timing violation fixing
The role involves performing timing analysis, optimization, and fixing timing violations at the chip and block level for SoCs

Job Summary

  • The role involves performing timing analysis, optimization, and fixing timing violations at the chip and block level for SoCs.
  • Candidates will work closely with clocking and backend teams to ensure clocking balance, timing fixes, and power delivery.
  • The position is based in Bangalore, India, within the Data Center Group focusing on Xeon-based solutions and AI-accelerated systems.

Matching Summary

The role involves performing timing analysis, optimization, and fixing timing violations at the chip and block level for SoCs.

Skills & Requirements

Must-have

  • Timing analysis and optimization
  • Timing constraint generation and verification
  • SoC timing violation fixing
  • Clock network design and balance
  • PVT condition definition

Nice-to-have

  • Collaboration with architecture teams
  • Flow development for chip integration
  • High performance low power guidelines
  • Efficient methodology development

Key Requirements

  • B.tech or M.tech degree required
  • Experienced hire status required
  • On-site presence required in Bangalore

Work Rights

Not specified

Tailored Resume

Cover Letter