Senior Post Silicon Dft Engineer

Intel

Haifa, Israel
Hybrid
Dft design engineer
Post silicon enabling
Scan and array infrastructure
This position is in Intel’s “center of excellence” for Silicon debug supporting Client products

Job Summary

  • This position is in Intel’s “center of excellence” for Silicon debug supporting Client products.
  • This team resolves product quality and performance issues blocking products from meeting production requirements with a combination of design and manufacturing problem solving expertise.
  • The Silicon Engineering Group (SIG) is a worldwide organization focused on the development and integration of SOCs, Cores, and critical IPs from architecture to manufacturing readiness.

Matching Summary

This position is in Intel’s “center of excellence” for Silicon debug supporting Client products.

Skills & Requirements

Must-have

  • DFT Design Engineer
  • Post Silicon enabling
  • Scan and Array infrastructure
  • Silicon debug
  • Client products

Nice-to-have

  • Hands-on problem solver
  • State of the art methodologies
  • Power-on and reset flow
  • Digital circuit design methodology

Key Requirements

  • BSC or MSC degree in Engineering
  • Previous semiconductor circuit design experience
  • Strong English communication skills
  • Previous DFT experience
  • Previous Scan and Array insertion experience

Work Rights

Not specified

Tailored Resume

Cover Letter