You will be in the Silicon One development organization as an ASIC Technical Lead in San Jose with a primary focus on Design-for-Test
Job Summary
You will be in the Silicon One development organization as an ASIC Technical Lead in San Jose with a primary focus on Design-for-Test.
Responsible for defining and implementing post-silicon strategies and implementing Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug and diagnostics needs of the designs.
At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond.
Matching Summary
You will be in the Silicon One development organization as an ASIC Technical Lead in San Jose with a primary focus on Design-for-Test.
Salary
Base: $210,600.00 - $305,100.00; Bonus/Equity: Not specified; Benefits: Medical, dental, vision, 401(k) with match, paid parental leave, disability, life insurance, restricted stock units, paid time away
Skills & Requirements
Must-have
post-silicon debug
Jtag protocols, Scan and BIST
ATE, in-system test, debug
DFT IP development
full chip design integration
gate level simulation debugging
Nice-to-have
innovative DFT solutions
re-usable test and debug strategies
collaboration with multi-functional teams
minimal mentorship debugging
Key Requirements
Bachelor's or Master's Degree in Electrical or Computer Engineering
at least 10 years of experience
Prior experience with ATPG and EDA tools
Prior experience working with Gate level simulation