Senior Static Timing Analysis (sta) Developer

Indclutch

San Jose, California, United States
$178.9k - $259.0k usd
Sta algorithms
Eda software development
Performance-driven optimization
Architect and develop high-performance STA engines for ASIC and FPGA design flows, enhancing graph-based timing analysis algorithms

Job Summary

  • Architect and develop high-performance STA engines for ASIC and FPGA design flows, enhancing graph-based timing analysis algorithms.
  • Optimize PPA-critical components and implement advanced data structures to support extremely large IC designs and modern compute architectures.
  • Support customer tape-outs by ensuring STA robustness, accuracy, and runtime efficiency, and contribute to product roadmap discussions.

Matching Summary

Architect and develop high-performance STA engines for ASIC and FPGA design flows, enhancing graph-based timing analysis algorithms.

Salary

$178.9K - $259.0K USD

Skills & Requirements

Must-have

  • STA algorithms
  • EDA software development
  • performance-driven optimization
  • large-scale IC designs
  • multi-threaded compute environments
  • C/C++ development skills

Nice-to-have

  • commercial STA tools experience
  • customer tape-outs support
  • disk-caching strategies
  • distributed computing

Key Requirements

  • 10+ years of experience in EDA software development
  • Strong focus on STA or timing-related engines
  • Deep understanding of static timing analysis concepts
  • Experience with multi-threading, memory optimization, and scalable software architecture
  • Proven ability to debug complex issues

Work Rights

Must be eligible for U.S. export authorizations

Tailored Resume

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