Senior Fpga / Rtl Design Engineer - Signal Processing

Silvus Technologies

Los Angeles, United States
$125,000—$195,000 usd py
On-site
Fixed point signal processing
Multi-clock domain fpga design
Xilinx fpgas and vivado ide
Participate in all aspects of the research and development process from concept to field deployment

Job Summary

  • Participate in all aspects of the research and development process from concept to field deployment.
  • Responsible for the efficient implementation of novel signal processing algorithms for Silvus' MIMO wireless networking products.
  • This position is based at Silvus Technologies’ headquarters in the heart of vibrant West Los Angeles, CA, and is on a hybrid schedule.

Matching Summary

Participate in all aspects of the research and development process from concept to field deployment.

Salary

$125,000—$195,000 USD

Skills & Requirements

Must-have

  • fixed point signal processing
  • multi-clock domain FPGA design
  • Xilinx FPGAs and Vivado IDE
  • hardware verification and troubleshooting

Nice-to-have

  • MATLAB experience
  • communication systems on FPGA/ASIC

Key Requirements

  • 6 years FPGA design experience (or MS with 4 years, or PhD with 2 years)
  • Bachelor of Science degree in EE, CS, or related
  • Must be U.S. Person

Work Rights

Must be U.S. Person

Tailored Resume

Cover Letter