Develop and maintain RTL designs using Verilog/System Verilog for FPGA and ASIC solutions and perform functional simulation and verification to ensure the designs meet functional and performance specifications
Job Summary
Develop and maintain RTL designs using Verilog/System Verilog for FPGA and ASIC solutions and perform functional simulation and verification to ensure the designs meet functional and performance specifications.
Collaborate closely with architects, verification engineers, and system teams to clarify requirements, and support design integration, bring-up, and issue resolution.
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.
Matching Summary
Develop and maintain RTL designs using Verilog/System Verilog for FPGA and ASIC solutions and perform functional simulation and verification to ensure the designs meet functional and performance specifications.
Skills & Requirements
Must-have
RTL design using Verilog/System Verilog
FPGA and ASIC solutions
Functional simulation and verification
Design integration and bring-up
Coding standards and documentation
Nice-to-have
Packet Based Protocols experience
Agentic AI experience
Logic analyzers and scopes
Embedded SW with NIOS or ARM
FPGA design and debug tools
Key Requirements
5+ years of experience in RTL/Logic design
Experience writing RTL in Verilog or System Verilog