Principal Engineer, Design Verification

Analog Devices

Newbury, United Kingdom
Uvm testbench development
System verilog verification
Constrained random techniques
The Design Verification Engineer will collaborate with the wider ADI technical community which affords an opportunity to work with many business units in ADI with exposure to many technologies and products

Job Summary

  • The Design Verification Engineer will collaborate with the wider ADI technical community which affords an opportunity to work with many business units in ADI with exposure to many technologies and products.
  • This position will be responsible for contributing to the verification of complex designs and sub-systems using leading edge verification methodologies.
  • Lead verification efforts at IP or SoC level, effort estimation, project scheduling and tracking, task assignment, reporting to management or customer.

Matching Summary

The Design Verification Engineer will collaborate with the wider ADI technical community which affords an opportunity to work with many business units in ADI with exposure to many technologies and products.

Skills & Requirements

Must-have

  • UVM testbench development
  • System Verilog verification
  • constrained random techniques
  • assertion based verification
  • formal verification techniques
  • debugging gate level simulation

Nice-to-have

  • customer facing experience
  • behavioral modelling of analogue circuits
  • low power methodologies
  • HW emulation or FPGA prototyping

Key Requirements

  • 10-15 years in ASIC design verification
  • Bachelor's or master’s degree in Engineering
  • Building and leading small verification teams
  • Strong level of English speaking and writing

Work Rights

Not specified

Tailored Resume

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