Senior Logic Design & Verification Engineer

Cisco UK

Rtl design experience with verilog/systemverilog
5+ years of relevant engineering experience
B.sc./m.sc. in electrical engineering
Engineers cover the full spectrum of chip design including definition, architecture, micro-architecture, RTL design, verification, signoff, and validation

Job Summary

  • Engineers cover the full spectrum of chip design including definition, architecture, micro-architecture, RTL design, verification, signoff, and validation.
  • The role involves writing micro-architecture specifications and implementing RTL to meet timing, performance, and power requirements.
  • Candidates will collaborate with verification and physical design teams to resolve bugs, achieve coverage closure, and close timing issues.

Matching Summary

Engineers cover the full spectrum of chip design including definition, architecture, micro-architecture, RTL design, verification, signoff, and validation.

Skills & Requirements

Must-have

  • RTL design experience with Verilog/SystemVerilog
  • 5+ years of relevant engineering experience
  • B.Sc./M.Sc. in Electrical Engineering

Nice-to-have

  • Experience with MATLAB simulations and bit-exact modeling
  • Familiarity with mixed-signal systems environments
  • Hands-on experience with Clock Domain Crossing (CDC)

Key Requirements

  • Minimum 5 years of experience in relevant field
  • B.Sc. or M.Sc. degree from a top university
  • Proven RTL design background required

Work Rights

Not specified

Tailored Resume

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