Senior Dft Timing Signoff Engineer (sta)

Intel Retiree Medical Plan Trust

Folsom, California, US
$164,470.00-269,100.00 usd py
**
Primetime-based dft-mode timing constraints
Tessent dft architecture and implementation
Streaming scan network (ssn) concepts
** Intel is seeking a Senior DFT Timing Signoff Engineer to join their Folsom, California team, focusing on ensuring the design and manufacturing of advanced AI processors. The role requires strong expertise in DFT architecture, PrimeTime-based signoff, and collaboration with various engineering teams to enhance silicon success. **

Job Summary

  • We are seeking a highly skilled and hands-on DFT/STA Engineer to join our full-chip timing organization supporting next-generation AI processors.
  • Own the definition, generation, validation, and maintenance of comprehensive DFT timing constraints (SDC) in Synopsys PrimeTime for modes including Scan Shift, Scan Capture (slow/fast as applicable), JTAG/IJTAG, and Memory BIST.
  • Improve DFT/STA flows through automation (Tcl required; Python/shell preferred): multi-mode runs, report triage, regression checks, and signoff dashboards.

Matching Summary

Match Score: 75

** Intel is seeking a Senior DFT Timing Signoff Engineer to join their Folsom, California team, focusing on ensuring the design and manufacturing of advanced AI processors. The role requires strong expertise in DFT architecture, PrimeTime-based signoff, and collaboration with various engineering teams to enhance silicon success. **

Salary

$164,470.00-269,100.00 USD

Skills & Requirements

Must-have

  • PrimeTime-based DFT-mode timing constraints
  • Tessent DFT architecture and implementation
  • Streaming Scan Network (SSN) concepts
  • IJTAG/test access integration (HTAP, TAPLink)
  • Memory test/repair (MBIST/BISR) fundamentals
  • Verilog/SystemVerilog for netlist debugging
  • Tcl scripting for automation

Nice-to-have

  • Python/shell scripting for automation
  • Low-power intent checks
  • Cross-team closure with PD and DFT stakeholders

Key Requirements

  • Bachelors & 8+ years or Masters & 6+ years in EE/CE
  • 6+ years in DFT and/or STA for complex SoCs
  • PrimeTime-only signoff environment experience
  • CDC/RDC fundamentals

Work Rights

Not specified

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