Define end-to-end DFT architecture and strategy for complex FPGA designs and platforms, driving DFT requirements at architecture and RTL definition stages
Job Summary
Define end-to-end DFT architecture and strategy for complex FPGA designs and platforms, driving DFT requirements at architecture and RTL definition stages.
Provide hands-on leadership for complex DFT implementations, including Scan Architecture, ATPG pattern generation, Cell-Aware, and Memory BIST.
Lead DFT design to collaborate with post-silicon team on silicon power on, debug, failure analysis, and yield improvement initiatives.
Matching Summary
Define end-to-end DFT architecture and strategy for complex FPGA designs and platforms, driving DFT requirements at architecture and RTL definition stages.
Skills & Requirements
Must-have
DFT architecture and strategy
DFT implementation and sign-off
Scan Architecture, ATPG
IEEE 1149.1 and IEEE 1687
DFT timing constraints
post-silicon debug and failure analysis
Nice-to-have
functional safety standards
AI or LLM for DFT enhancement
low-power DFT solutions
scripting and automation skills
Key Requirements
Bachelor’s or Master’s degree
10+ years of industry experience in DFT design
Strong experience in DFT methodology, architecture & design