Ip Design Verification Engineer

Intel Retiree Medical Plan Trust

Hillsboro, Oregon, US
Base: $122,440.00-232,190.00 usd; bonus/equity: st...
Hybrid
System verilog & uvm testbench development
Verification environments with coverage metrics
Constrained-random stimulus
Perform comprehensive functional verification of IP or subsystem logic blocks to ensure compliance with specification requirements

Job Summary

  • Perform comprehensive functional verification of IP or subsystem logic blocks to ensure compliance with specification requirements.
  • Develop and execute detailed verification plans, test benches, and verification environments with comprehensive coverage metrics.
  • We offer a total compensation package that ranks among the best in the industry.

Matching Summary

Perform comprehensive functional verification of IP or subsystem logic blocks to ensure compliance with specification requirements.

Salary

Base: $122,440.00-232,190.00 USD; Bonus/Equity: stock bonuses; Benefits: health, retirement, and vacation

Skills & Requirements

Must-have

  • System Verilog & UVM testbench development
  • Verification environments with coverage metrics
  • Constrained-random stimulus
  • Debugging presilicon environments
  • Python or other scripting language
  • Synopsys VCS, Cadence Xcelium, or Mentor Questa
  • Git, Perforce version control

Nice-to-have

  • AI/ML-driven verification
  • Power-aware verification
  • CPU/GPU architecture verification
  • Emulation platforms

Key Requirements

  • 6+ years of experience in digital design verification
  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related technical field
  • 5+ years of experience in IP or SoC verification environments (Master's degree)

Work Rights

Not specified

Tailored Resume

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