Senior Asic Timing Engineer

NVIDIA

Base: 168,000 usd - 264,500 usd (level 4); 196,000...
Static timing analysis (sta)
Timing convergence
Timing constraints generation
Lead the timing analysis and closure processes for Nvidia’s GPUs, CPUs, DPUs, and SoCs at block level, cluster level, and full chip level

Job Summary

  • Lead the timing analysis and closure processes for Nvidia’s GPUs, CPUs, DPUs, and SoCs at block level, cluster level, and full chip level.
  • Work closely with RTL, DFX, Clocks, and other teams to devise timing closure strategies, create timing constraints, and drive timing and power convergence as well as implement ECOs.
  • Leverage your expertise to improve timing convergence flows in collaboration with methodology teams.

Matching Summary

Lead the timing analysis and closure processes for Nvidia’s GPUs, CPUs, DPUs, and SoCs at block level, cluster level, and full chip level.

Salary

Base: 168,000 USD - 264,500 USD (Level 4); 196,000 USD - 310,500 USD (Level 5); Bonus/Equity: equity; Benefits: benefits

Skills & Requirements

Must-have

  • Static Timing Analysis (STA)
  • timing convergence
  • timing constraints generation
  • physical design optimization
  • deep sub-micron process nodes

Nice-to-have

  • logic synthesis
  • DFT timing closure
  • AMS designs/IPs timing closure
  • methodology development
  • automation

Key Requirements

  • BS or equivalent experience with 8 years
  • MS or equivalent experience with 2 years
  • Hands-on experience in full-chip/sub-chip STA
  • Expertise in analysis and fixing of timing paths through ECOs
  • Expertise and in-depth knowledge of industry standard STA tools

Work Rights

Not specified

Tailored Resume

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