Sr. Principal Design Engineer

Cadence

12+ years analog mixed-signal ic design experience
High-speed interface design (ddr, pcie, serdes)
Ucie standard concepts and d2d phy requirements
The role involves driving the architecture through silicon bring-up for high-speed Die-to-Die interconnects based on the UCIe standard

Job Summary

  • The role involves driving the architecture through silicon bring-up for high-speed Die-to-Die interconnects based on the UCIe standard.
  • Candidates will own analog blocks including clocking, TX/RX front-ends, and equalization circuits while collaborating with package teams.
  • Success requires robust ownership from initial feasibility analysis to post-layout sign-off and full-chip integration validation.

Matching Summary

The role involves driving the architecture through silicon bring-up for high-speed Die-to-Die interconnects based on the UCIe standard.

Skills & Requirements

Must-have

  • 12+ years analog mixed-signal IC design experience
  • High-speed interface design (DDR, PCIe, SerDes)
  • UCIe standard concepts and D2D PHY requirements
  • Advanced packaging technologies (2.5D/3D, interposers)
  • Schematic design simulation optimization across PVT corners

Nice-to-have

  • Direct hands-on UCIe PHY design or integration
  • Post-silicon debug and correlation experience
  • Power integrity and thermal considerations knowledge
  • Mentoring junior engineers and leading technical discussions
  • AMS verification flows exposure

Key Requirements

  • Bachelor's or Master's degree in Electrical/Electronics Engineering
  • 12+ years of hands-on experience in analog/mixed-signal IC design
  • Strong fundamentals in signal integrity and noise analysis

Work Rights

Not specified

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