Not specified (assumed hybrid based on industry norms).
End-to-end dft architecture definition
Scan insertion and atpg execution
Memory bist and logic bist strategies
Analog Devices is seeking a Staff DFT Engineer to lead the design-for-test (DFT) strategy for complex system-on-chips (SoCs). The role requires extensive experience in DFT methodologies and technical leadership skills, with responsibilities spanning from architecture definition through to production support
Job Summary
This role requires owning the complete DFT strategy for complex SoCs from architecture through production silicon.
The ideal candidate will lead end-to-end implementation including scan insertion, ATPG, and signoff while balancing coverage and power tradeoffs.
Candidates must demonstrate deep expertise in LBIST, MBIST, and boundary scan while mentoring junior engineers and collaborating cross-functionally.
Matching Summary
Match Score: 85
Analog Devices is seeking a Staff DFT Engineer to lead the design-for-test (DFT) strategy for complex system-on-chips (SoCs). The role requires extensive experience in DFT methodologies and technical leadership skills, with responsibilities spanning from architecture definition through to production support.
Skills & Requirements
Must-have
End-to-end DFT architecture definition
Scan insertion and ATPG execution
Memory BIST and Logic BIST strategies
Test compression and pattern optimization
Silicon bring-up and yield ramp support
Cross-functional collaboration with PD teams
Nice-to-have
High-volume production test experience
Safety-critical application exposure
On-chip debug and trace features
Python/Tcl/Perl scripting automation
Mentoring junior engineering talent
Key Requirements
7+ years hands-on DFT experience
Bachelor's or Master's degree in Electrical Engineering
Proven leadership of end-to-end SoC execution
Proficiency with Cadence and Siemens EDA tools
Work Rights
Citizenship or Green Card required for export control compliance