The role involves performing IC design development for SerDes IP products including logic synthesis and static timing analysis
Job Summary
The role involves performing IC design development for SerDes IP products including logic synthesis and static timing analysis.
Candidates must lead DFT activities such as scan insertion, ATPG, and pattern validation while collaborating with physical designers for timing closure.
Successful applicants will debug functional issues in taped-out devices and support ISO processes alongside customer systems engineers.
Matching Summary
Match Score: 85
The role involves performing IC design development for SerDes IP products including logic synthesis and static timing analysis.
Skills & Requirements
Must-have
5 years digital IC design experience
Verilog HDL and VHDL RTL design
Logic Synthesis and Static Timing Analysis
DFT Scan Insertion and ATPG
Design to tape-out experience
Cadence and Synopsys EDA tools
Nice-to-have
Digital and mixed-signal design knowledge
USB interface product experience
Graphics processor and driver products
Connectivity technology expertise
Strong communication skills
Self-motivated team player
Key Requirements
Degree or Master in Electrical Electronic Engineering