【SBT】パッケージ基板技術開発 エンジニア

TSMC Japan 3DIC R&D Center, Inc

Tsukuba, Ibaraki, Japan
Base: based on current annual income; bonus: twice...
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3+ years semiconductor industry experience
Technical problem-solving skills
Bachelor's degree or higher in engineering
** TSMC Japan 3DIC R&D Center is seeking an experienced engineer for semiconductor packaging technology development. This role focuses on maximizing the performance, reliability, and efficiency of semiconductor packages, requiring collaboration with diverse teams and suppliers. **

Job Summary

  • This role involves developing fundamental technologies to maximize the performance, reliability, and manufacturing efficiency of semiconductor packages at TSMC's Japan R&D Center.
  • Candidates will collaborate with diverse teams and domestic/international suppliers to create innovative next-generation 3D IC and CoWoS® packaging solutions.
  • The position offers a competitive salary based on current income, twice-yearly bonuses, and comprehensive benefits including health insurance and a defined contribution pension plan.

Matching Summary

Match Score: 75

** TSMC Japan 3DIC R&D Center is seeking an experienced engineer for semiconductor packaging technology development. This role focuses on maximizing the performance, reliability, and efficiency of semiconductor packages, requiring collaboration with diverse teams and suppliers. **

Salary

Base: Based on current annual income; Bonus: Twice yearly (Summer/Winter) plus performance-based annual bonus; Benefits: Commuting allowance up to 100,000 JPY/month, overtime pay, retirement fund matching

Skills & Requirements

Must-have

  • 3+ years semiconductor industry experience
  • Technical problem-solving skills
  • Bachelor's degree or higher in engineering
  • Japanese JLPT N2 proficiency
  • TOEIC 650+ or equivalent English experience

Nice-to-have

  • Independent R&D challenge setting
  • Japanese JLPT N1 proficiency
  • Experience with DOE and process window evaluation
  • Collaboration with international suppliers
  • Background in build-up dielectrics or solder resists

Key Requirements

  • 3 years minimum experience in semiconductor industry
  • Engineering degree (Bachelor, Master, or PhD)
  • Japanese Language Proficiency Test N2 required
  • English communication capability (TOEIC 650+ or proven experience)

Work Rights

Not specified

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