Senior Rtl Design Engineer

Cisco UK

Yerevan, Armenia
Hybrid
Verilog/system verilog coding
Front-end asic tools
Industry standard interface protocols
Join the Silicon One Team at Cisco in Armenia, a group at the forefront of developing Cisco's groundbreaking silicon architecture

Job Summary

  • Join the Silicon One Team at Cisco in Armenia, a group at the forefront of developing Cisco's groundbreaking silicon architecture.
  • As a key technical leader, you will drive next-generation silicon architecture development, guide your team in delivering solutions that power advanced global networks, and lead collaboration across multiple teams.
  • At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond.

Matching Summary

Join the Silicon One Team at Cisco in Armenia, a group at the forefront of developing Cisco's groundbreaking silicon architecture.

Skills & Requirements

Must-have

  • Verilog/System Verilog coding
  • front-end ASIC tools
  • industry standard interface protocols
  • Python, Tcl, Make scripting
  • RTL code review and enhancement
  • debug complex verification failures

Nice-to-have

  • familiarity with power optimization techniques
  • good communication skills
  • self-motivated and well-organized

Key Requirements

  • 6+ years ASIC digital design experience
  • Proficient in Verilog/System Verilog
  • Experience with front-end tools
  • Experience with AMBA, JTAG, memories
  • Ability to write scripts
  • Familiarity with power optimization techniques
  • Familiarity with DFT/MBIST is a plus

Work Rights

Not specified

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