This role involves leading the architecture and integration of complex SoC-wide clocking networks to optimize power-performance-area trade-offs
Job Summary
This role involves leading the architecture and integration of complex SoC-wide clocking networks to optimize power-performance-area trade-offs.
The successful candidate will mentor a team while collaborating cross-functionally with RTL, physical design, and verification teams to deliver end-to-end silicon solutions.
You will partner with foundries and EDA vendors to ensure robust silicon correlation, yield, and high-reliability signoff for transformative AI and networking technologies.
Matching Summary
This role involves leading the architecture and integration of complex SoC-wide clocking networks to optimize power-performance-area trade-offs.
Salary
Not specified; Not specified; Not specified
Skills & Requirements
Must-have
SoC clocking network architecture
PLL and DLL design expertise
Transistor-level circuit design
Clock tree synthesis and gating
Glitch-free domain crossing
Spice simulation and validation
Nice-to-have
High-speed interface IP background
Server or AI/ML SoC experience
Silicon bring-up and debug skills
Patents in circuit design
Custom memory design knowledge
Key Requirements
M.Tech / B.Tech / Ph.D. in Electrical Engineering
15–20 years hands-on SoC clocking experience
Deep expertise in custom analog/digital circuit design
Experience leading multi-disciplinary global teams