Dft Rtl Design And Integration Engineer

Intel Retiree Medical Plan Trust

Petah-Tikva, Israel
Hybrid
5+ years design-for-test experience
2+ years scan insertion experience
Linux environment proficiency
The role involves developing logic design, RTL coding, and providing DFT timing closure support for SoC integration

Job Summary

  • The role involves developing logic design, RTL coding, and providing DFT timing closure support for SoC integration.
  • Candidates will define and implement SoC main debug fabrics including TAP and Scan while working closely with Architecture and Manufacturing teams.
  • This position requires driving coverage improvement, reducing DPM, and enabling content on both Pre-Si environments and real Silicon.

Matching Summary

The role involves developing logic design, RTL coding, and providing DFT timing closure support for SoC integration.

Skills & Requirements

Must-have

  • 5+ years Design-for-Test experience
  • 2+ years Scan insertion experience
  • Linux environment proficiency
  • RTL coding and simulation skills
  • SoC debug fabrics implementation

Nice-to-have

  • Automatic tool development capabilities
  • Cross-functional collaboration with Architecture
  • Experience with Silicon validation flows
  • Power, Performance, Test Time optimization

Key Requirements

  • Bachelor's degree in Electrical Engineering or related field
  • Minimum 5 years of DFT methodology experience
  • Minimum 2 years hands-on Scan insertion experience
  • Proficiency in Linux environments

Work Rights

Not specified

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