The role involves leading the definition and implementation of micro-architecture and RTL for high-speed digital designs in next-generation IO technologies
Job Summary
The role involves leading the definition and implementation of micro-architecture and RTL for high-speed digital designs in next-generation IO technologies.
Candidates must possess strong communication and leadership skills to work closely with verification and back-end teams for validation and timing closure.
Responsibilities include supporting post-silicon debug and characterization while ensuring compliance with power gating and SDC standards.
Matching Summary
The role involves leading the definition and implementation of micro-architecture and RTL for high-speed digital designs in next-generation IO technologies.
Skills & Requirements
Must-have
10 years ASIC frontend experience
RTL coding using HDL languages
High speed digital design implementation
Synthesis STA and physical implementation knowledge
Post silicon debug and characterization support
Nice-to-have
Strong communication and leadership skills
Scripting language proficiency
Problem solving and analytical abilities
Collaboration with verification teams
Key Requirements
BS/MS or PhD in Electronics Engineering
Minimum 10 years of ASIC frontend experience
Proficiency with Spyglass Synthesis STA PT UPF UVM Spice DFT