Develop performance models, perform architectural tradeoff analysis, and enable data driven design decisions for next generation DDR memory controller architectures
Job Summary
Develop performance models, perform architectural tradeoff analysis, and enable data driven design decisions for next generation DDR memory controller architectures.
Develop cycle-level performance models in SystemC or C++ and correlate them to match RTL configurations and traffic conditions.
Develop scripts to automate generation of various performance metrics and statistics post RTL simulation that helps identify performance bottlenecks.
Matching Summary
Develop performance models, perform architectural tradeoff analysis, and enable data driven design decisions for next generation DDR memory controller architectures.