Principal Physical Design Engineer (rtl-to-gdsii)

Enchargeai36

Bangalore, India
On-site
Rtl-to-gdsii physical design
Sub-5nm technology nodes
Cadence digital suite mastery
Lead the implementation of massive, high-speed blocks/SoCs from Synthesis through Sign-off using the Cadence Digital Suite

Job Summary

  • Lead the implementation of massive, high-speed blocks/SoCs from Synthesis through Sign-off using the Cadence Digital Suite.
  • Build and refine a "Push-Button" style execution methodology that is robust, repeatable, and minimizes manual "human-in-the-loop" iterations.
  • Collaborate with RTL, Architecture, and DFT teams to influence design decisions early.

Matching Summary

Lead the implementation of massive, high-speed blocks/SoCs from Synthesis through Sign-off using the Cadence Digital Suite.

Skills & Requirements

Must-have

  • RTL-to-GDSII physical design
  • Sub-5nm technology nodes
  • Cadence Digital Suite mastery
  • PPA optimization
  • Tcl and Python scripting

Nice-to-have

  • First Principles thinker
  • Holistic thinking
  • Cross-functional collaboration
  • Methodology development

Key Requirements

  • 14+ years in Physical Design
  • Multiple sub-5nm tape-outs
  • Mastery of Cadence Innovus, Tempus, Joules, Pegasus, and Voltus
  • Expert-level STA, PV, PI, and ECO methodology

Work Rights

Not specified

Tailored Resume

Cover Letter