Collaborate with architects and design engineers to understand IP specifications and define comprehensive verification strategies and detailed test plans
Job Summary
Collaborate with architects and design engineers to understand IP specifications and define comprehensive verification strategies and detailed test plans.
Develop robust, reusable, and constrained-random verification environments using SystemVerilog and UVM (Universal Verification Methodology).
Define and track functional and code coverage metrics to ensure verification completeness and drive coverage closure.
Matching Summary
Collaborate with architects and design engineers to understand IP specifications and define comprehensive verification strategies and detailed test plans.
Skills & Requirements
Must-have
SystemVerilog and UVM
coverage-driven verification
assertion-based verification
simulation and debug tools
Python, Perl, or Tcl scripting
Nice-to-have
collaborative, cross-functional team environment
analytical, problem-solving, and debugging skills
familiarity with industry-standard protocols
Key Requirements
3+ years of experience in ASIC or FPGA design verification
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field