Senior Design Verification Engineer

Intel

Bangalore, India
Design verification engineer
Ip and subsystem level verification
Uvm, sva, and abv methodologies
Independently own verification of interconnect and chassis IP blocks from planning through coverage closure, operating with minimal guidance

Job Summary

  • Independently own verification of interconnect and chassis IP blocks from planning through coverage closure, operating with minimal guidance.
  • Build scalable verification environments with reusable testbenches, checkers, constrained-random tests, and debug infrastructure.
  • Collaborate closely with architecture, design, and software teams on spec reviews, feature clarification, bug triage, and closure.

Matching Summary

Independently own verification of interconnect and chassis IP blocks from planning through coverage closure, operating with minimal guidance.

Skills & Requirements

Must-have

  • Design Verification Engineer
  • IP and subsystem level verification
  • UVM, SVA, and ABV methodologies
  • SystemVerilog/UVM, C/C++, Python
  • Interconnects and bus protocols
  • AI-assisted development tools

Nice-to-have

  • Formal verification tools
  • Emulation or FPGA-based verification
  • Global functions verification
  • RTL concepts, physical design

Key Requirements

  • 8-12 years of relevant experience
  • BS/MS in Electrical Engineering, Computer Science, or related field
  • Solid background in IP-level DV
  • Meaningful exposure to subsystem-level verification
  • Working understanding of cache coherency
  • Ability to mentor junior engineers

Work Rights

Not specified

Tailored Resume

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