Asic Design Verification Engineer

Ericsson

Austin, Texas, United States
Not specified; annual bonus based on performance; ...
On-site
Systemverilog and uvm experience
Block and top-level asic verification
Testbench architecture from scratch
You will join a world-class semiconductor team building the backbone of next-generation 5G networks

Job Summary

  • You will join a world-class semiconductor team building the backbone of next-generation 5G networks.
  • Your role involves owning coverage closure from block to chip and designing UVM environments from scratch.
  • Ericsson offers a competitive package including health benefits, 401(k) matching, and up to 16 weeks of paid maternity leave.

Matching Summary

You will join a world-class semiconductor team building the backbone of next-generation 5G networks.

Salary

Not specified; Annual bonus based on performance; Competitive package with 401(k) match and health benefits

Skills & Requirements

Must-have

  • SystemVerilog and UVM experience
  • Block and Top-Level ASIC verification
  • Testbench architecture from scratch
  • RTL debug experience
  • Scripting proficiency in TCL Python Perl

Nice-to-have

  • Embedded software design experience
  • Leadership instincts and growth hunger
  • AMBA APB AXI interface familiarity
  • Computer architecture knowledge
  • Linux GIT LSF environment fluency

Key Requirements

  • Several years of industry RTL verification experience
  • Bachelor's or Master's degree in Electrical or Computer Engineering
  • Hands-on experience with IP verification in ASIC SoC

Work Rights

Not specified

Tailored Resume

Cover Letter