Shape hardware around the model before a single transistor is placed, occupying the most strategically critical seat in the silicon program
Job Summary
Shape hardware around the model before a single transistor is placed, occupying the most strategically critical seat in the silicon program.
Take bleeding-edge AI and RAN algorithms and convert them into precise hardware specifications and concrete lowering requirements.
Project performance using cycle-accurate simulators and SystemC models to give the silicon team confidence for multi-million dollar tape-out decisions.
Matching Summary
Shape hardware around the model before a single transistor is placed, occupying the most strategically critical seat in the silicon program.
Skills & Requirements
Must-have
Transformer architecture mastery
Hardware-aware ML thinking
JAX/PyTorch export/compilation
Cycle-accurate performance projection
Model partitioning and tiling strategies
Nice-to-have
Applied AI to RAN workloads
Understanding of MLIR compiler journey
Experience with complex-valued AI models
Key Requirements
Deep knowledge of Transformer architectures
Experience with hardware-in-the-loop
Advanced proficiency in JAX, PyTorch, or TensorFlow
Performance modeling experience (SystemC, TLM)
Experience with real RAN workloads (preferred)
Understanding of MLIR transformation passes (preferred)
Hands-on experience with complex-valued AI models (preferred)