$117,000 to $175,000; annual bonus; excellent heal...
On-site
Systemverilog/verilog rtl design
Asic/ip development flow
Dsp/fec algorithm implementation
Join Ericsson’s Accelerator IP team in Austin, TX as a Senior RTL Design Engineer and own the microarchitecture of next‑generation L1 accelerators from blank page to silicon
Job Summary
Join Ericsson’s Accelerator IP team in Austin, TX as a Senior RTL Design Engineer and own the microarchitecture of next‑generation L1 accelerators from blank page to silicon.
Transform high-level architectural vision into blazing-fast, reliable RTL (SystemVerilog/Verilog) and take complete ownership of major IP blocks—specification, microarchitecture, RTL creation, synthesis, and delivery.
Ericsson offers a competitive package including a salary range of $117,000 to $175,000, annual bonus opportunities, excellent health benefits, 401(k) with company contributions, and generous paid time off.
Matching Summary
Join Ericsson’s Accelerator IP team in Austin, TX as a Senior RTL Design Engineer and own the microarchitecture of next‑generation L1 accelerators from blank page to silicon.
Salary
$117,000 to $175,000; Annual bonus; Excellent health benefits, 401(k) with company contributions, generous PTO
Skills & Requirements
Must-have
SystemVerilog/Verilog RTL design
ASIC/IP development flow
DSP/FEC algorithm implementation
Power/area/throughput optimization
End-to-end IP ownership
Nice-to-have
Collaborative and creative environment
Shaping world-class telecom products
Autonomy and impact
Key Requirements
Several years of RTL design experience
Expert SystemVerilog/Verilog skills
End-to-end ASIC flow mastery
Proven ability to distill algorithms into hardware