Principal Design Engineer- Memory Ip

Cadence

San Jose, California, US
Base: $136,500 to $253,500; bonus/equity: incentiv...
Logic design and micro-architecture
Verilog/systemverilog simulation environment
High speed and low power ic design
Proficiency in logic design and micro-architecture, Verilog/SystemVerilog, and its simulation environment is essential

Job Summary

  • Proficiency in logic design and micro-architecture, Verilog/SystemVerilog, and its simulation environment is essential.
  • The role requires at least six years of experience in digital IC development projects and strong communication skills.
  • Benefits programs include paid vacation, 401(k) plan with employer match, and a variety of medical, dental, and vision plan options.

Matching Summary

Proficiency in logic design and micro-architecture, Verilog/SystemVerilog, and its simulation environment is essential.

Salary

Base: $136,500 to $253,500; Bonus/Equity: incentive compensation (bonus, equity); Benefits: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, medical, dental, and vision plan options

Skills & Requirements

Must-have

  • logic design and micro-architecture
  • Verilog/SystemVerilog simulation environment
  • high speed and low power IC design
  • JEDEC-DDR and DFI protocols

Nice-to-have

  • lead and contribute in a cooperative team
  • make an impact on the world of technology

Key Requirements

  • BS degree with 8+ years of experience
  • MS degree with 6+ years of experience
  • memory IP design experience

Work Rights

Not specified

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