Rtl Design Lead Hardware Engineer

Altera Corporation

Bengaluru, Karnataka, India
Rtl design using vhdl/verilog/system verilog
Digital design and timing closure
Fpga debug environment tools
As a Hardware Engineer, you will be responsible for the development of RTL for various soft IPs, including on-chip Memory Mapped Interconnect and streaming protocols IPs

Job Summary

  • As a Hardware Engineer, you will be responsible for the development of RTL for various soft IPs, including on-chip Memory Mapped Interconnect and streaming protocols IPs.
  • You will lead a team of dedicated RTL design Engineers to build soft IPs for Altera FPGAs and develop new interconnect topologies to maximize data transfer throughput.
  • The role involves working closely with developers across software, IP and embedded engineering to ensure design flows meet customer needs and guiding IP release content.

Matching Summary

As a Hardware Engineer, you will be responsible for the development of RTL for various soft IPs, including on-chip Memory Mapped Interconnect and streaming protocols IPs.

Skills & Requirements

Must-have

  • RTL design using VHDL/Verilog/System Verilog
  • Digital design and timing closure
  • FPGA debug environment tools
  • On-chip interconnect protocols (AXI/APB/AHB/Avalon)
  • Streaming protocols (AXI/Avalon)
  • Lead RTL design engineers

Nice-to-have

  • Customer experience and usability focus
  • Influence across organization boundaries
  • Tcl, Perl, and/or Python scripting skills
  • Knowledge of Quartus or Vivado tool flow

Key Requirements

  • 10+ years of relevant industry experience
  • BS/MS/PhD degree in Electrical/Computer/Software Engineering or equivalent
  • Strong experience in Verilog and System Verilog
  • Understanding of Computer Architecture
  • ARM Based Bus Protocols knowledge

Work Rights

Not specified

Tailored Resume

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