Principal Asic Design Engineer (starshield)

SpaceX

Palo Alto, CA, United States
Base: $210,000.00 - $295,000.00/py; bonus/equity: ...
On-site
Rtl implementation in verilog/system verilog
Fpga/asic development
Digital asic and fpga design
As an ASIC Design Engineer on the Starshield team, you will be working on advanced development programs in support of U.S. National Security

Job Summary

  • As an ASIC Design Engineer on the Starshield team, you will be working on advanced development programs in support of U.S. National Security.
  • In this role, you will be developing cutting-edge next-generation FPGAs and ASICs for deployment in space and ground infrastructures around the globe.
  • You will receive access to comprehensive medical, vision, and dental coverage, access to a 401(k) retirement plan, short and long-term disability insurance, life insurance, paid parental leave, and various other discounts and perks.

Matching Summary

As an ASIC Design Engineer on the Starshield team, you will be working on advanced development programs in support of U.S. National Security.

Salary

Base: $210,000.00 - $295,000.00/per year; Bonus/Equity: Long-term incentives (stock, options, cash awards), discretionary bonuses, ESPP; Benefits: Medical, vision, dental, 401(k), disability, life insurance, paid parental leave, paid holidays, paid vacation

Skills & Requirements

Must-have

  • RTL implementation in Verilog/System Verilog
  • FPGA/ASIC development
  • Digital ASIC and FPGA design
  • Micro-architecture definition
  • Silicon bring-up and validation

Nice-to-have

  • Solving clock domain crossings
  • Power optimization techniques
  • High speed and low power design
  • Team-player, can-do attitude
  • Enjoy being challenged and learning

Key Requirements

  • Bachelor's degree in EE, CE, or CS
  • 10+ years of experience
  • Active TS-SCI clearance may be required

Work Rights

US citizen, permanent resident, refugee, or asylee

Tailored Resume

Cover Letter