Senior Soc Integration Engineer

Altera

Penang, Malaysia
Physical design flow
Synthesis, place and route
Static timing analysis
Performs physical design implementation of custom IP and SoC designs from RTL to GDS to create a design database that is ready for manufacturing

Job Summary

  • Performs physical design implementation of custom IP and SoC designs from RTL to GDS to create a design database that is ready for manufacturing.
  • Conducts all aspects of the physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis.
  • Possesses design optimization knowledge to improve product-level parameters such as power, frequency, and area.

Matching Summary

Performs physical design implementation of custom IP and SoC designs from RTL to GDS to create a design database that is ready for manufacturing.

Skills & Requirements

Must-have

  • physical design flow
  • synthesis, place and route
  • static timing analysis
  • power/clock distribution
  • formal equivalence verification
  • layout verification
  • deep submicron process nodes

Nice-to-have

  • low power design methodologies
  • power intent UPF specifications
  • scripting languages expertise
  • mentoring junior team members

Key Requirements

  • 5+ years relevant experience
  • multiple tape-out experience
  • physical design signoff flow
  • scripting languages (Perl, TCL, Python)
  • VHDL and Verilog knowledge

Work Rights

Not specified

Tailored Resume

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