Asic Physical Design Technical Lead

Cisco UK

Base: $183,800.00 - $263,600.00; bonus/equity: ann...
Not specified
Fullchip floorplan and hierarchical implementation
Rtl-to-gdsii flow in 7nm/5nm/3nm processes
Innovus tempus primetime redhawk voltus calibre tools
Cisco UK is seeking an Asic Physical Design Technical Lead to join their Common Hardware Group, responsible for designing networking hardware and ASICs for various sectors. The ideal candidate should have extensive experience in physical design, particularly in fullchip activities, and proficiency with EDA tools

Job Summary

  • This role involves designing the fullchip floorplan and implementing hierarchical flows for Cisco's Silicon One architecture spanning switches to data centers.
  • Candidates will lead RTL-to-GDSII implementation including place and route, static timing analysis, and power integrity optimization using industry-standard EDA tools.
  • The position offers competitive compensation ranging from $183,800 to $263,600 plus equity, bonuses, and comprehensive benefits including flexible vacation time.

Matching Summary

Match Score: 85

Cisco UK is seeking an Asic Physical Design Technical Lead to join their Common Hardware Group, responsible for designing networking hardware and ASICs for various sectors. The ideal candidate should have extensive experience in physical design, particularly in fullchip activities, and proficiency with EDA tools.

Salary

Base: $183,800.00 - $263,600.00; Bonus/Equity: Annual bonuses and restricted stock units available; Benefits: Medical, dental, vision, 401(k) match, paid parental leave, flexible vacation

Skills & Requirements

Must-have

  • Fullchip floorplan and hierarchical implementation
  • RTL-to-GDSII flow in 7nm/5nm/3nm processes
  • Innovus Tempus Primetime Redhawk Voltus Calibre tools
  • UPF low-power design methodologies
  • Custom clock mesh and Flex-HTree methods

Nice-to-have

  • Experience with AI tools for productivity improvement
  • Python scripting for flow automation
  • Post-Silicon Validation feedback integration
  • Foundry and IP vendor collaboration experience

Key Requirements

  • Bachelor's degree + 8 years or Master's + 6 years Physical Design experience
  • PhD in Electrical Engineering with 3+ years experience
  • Proven experience with tapeouts in 7nnm/5nm/3nm or below technologies
  • Proficiency with Innovus, Tempus/Primetime, Redhawk/Voltus, or Calibre/Pegasus

Work Rights

Not specified

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