Master's student in electrical or computer engineering
Familiarity with core rdma operations
Hands-on experience with mellanox connectx-7 tools
Intel DCG China is seeking a Research Intern to contribute to the development of Scale-up Protocols and Memory Pooling for KV Cache-Centric Systems in Shanghai. The ideal candidate will be a Master's student in a related field with hands-on experience in RDMA operations and GPU interconnect protocols
Job Summary
The role focuses on exploring architectural innovations for disaggregated AI supernode designs to optimize cost and scalability.
Candidates will research and prototype Ethernet-native GPU interconnect protocols and distributed memory pooling mechanisms.
This is an on-site internship position located in Shanghai, China, requiring a Master's degree in a related engineering field.
Matching Summary
Match Score: 85
Intel DCG China is seeking a Research Intern to contribute to the development of Scale-up Protocols and Memory Pooling for KV Cache-Centric Systems in Shanghai. The ideal candidate will be a Master's student in a related field with hands-on experience in RDMA operations and GPU interconnect protocols.
Skills & Requirements
Must-have
Master's student in Electrical or Computer Engineering
Familiarity with core RDMA operations
Hands-on experience with Mellanox ConnectX-7 tools
Working knowledge of LLM inference benchmarking
Nice-to-have
Passionate and self-motivated attitude
Experience with vLLM or lm-evaluation-harness frameworks
Understanding of system-level performance trade-offs