Principal Application Engineer

BETA CAE Systems International AG

Shanghai, China
Physical design implementation
Timing closure
Physical verification
The candidate will perform the physical design implementation, including floor planning, power grid design, place and route, clock tree synthesis, timing closure, power/signal integrity signoff, physical verification (DRC/LVS/Antenna), EM/IR signoff, DFM Closure

Job Summary

  • The candidate will perform the physical design implementation, including floor planning, power grid design, place and route, clock tree synthesis, timing closure, power/signal integrity signoff, physical verification (DRC/LVS/Antenna), EM/IR signoff, DFM Closure.
  • The candidate will have the opportunity to work on many varieties of challenging designs, i.e. low power and high speed designs at the latest technology nodes.
  • The candidate will work closely with RTL design team to ensure successful tapeouts.

Matching Summary

The candidate will perform the physical design implementation, including floor planning, power grid design, place and route, clock tree synthesis, timing closure, power/signal integrity signoff, physical verification (DRC/LVS/Antenna), EM/IR signoff, DFM Closure.

Skills & Requirements

Must-have

  • physical design implementation
  • timing closure
  • physical verification
  • EM/IR signoff
  • DFM Closure
  • low power and high speed designs

Nice-to-have

  • work independently
  • hands-on at all levels
  • self-motivated
  • team player
  • good English communication skills

Key Requirements

  • BS/MS in EE/CS
  • 3+ years of hands-on experience
  • experienced with ASIC design flow
  • understand deep sub-micron technology issues
  • solid knowledge on Low Power Design, DFT, static timing analysis and closure

Work Rights

Not specified

Tailored Resume

Cover Letter