Not specified; competitive pyckage with 3% compyny...
On-site
Deep systemverilog/verilog expertise
Enterprise-scale rtl methodology leadership
Spyglass lint and cdc analysis mastery
This role serves as the driving force behind scalable frontend design methodologies deployed across global engineering teams to power Ericsson's next-generation 5G portfolio
Job Summary
This role serves as the driving force behind scalable frontend design methodologies deployed across global engineering teams to power Ericsson's next-generation 5G portfolio.
The successful candidate will pioneer the integration of artificial intelligence into silicon design, focusing on AI-accelerated code generation and intelligent static analysis.
Ericsson offers a competitive benefits package including automatic 401(k) matching, up to 16 weeks of paid maternity leave, and comprehensive health coverage options.
Matching Summary
This role serves as the driving force behind scalable frontend design methodologies deployed across global engineering teams to power Ericsson's next-generation 5G portfolio.
Salary
Not specified; Competitive package with 3% company contribution plus match up to 4%; Includes medical/dental credits and 16 weeks paid maternity leave
Skills & Requirements
Must-have
Deep SystemVerilog/Verilog expertise
Enterprise-scale RTL methodology leadership
SpyGlass lint and CDC analysis mastery
UPF-aware low-power design experience
Python scripting and CI/CD pipeline deployment
AI/ML application to RTL productivity
Nice-to-have
Hands-on microarchitecture development skills
Global engineering team collaboration
Passion for next-generation silicon innovation
Experience with multi-program reuse strategies
Key Requirements
Proven leadership in enterprise-scale RTL methodologies
Expert command of SpyGlass and Synopsys VC Lint
Extensive knowledge of CDC analysis and static quality gates
Strong Python and automation framework skills
Hands-on experience with UPF-aware design strategies