Sr Principal Program Manager

Cadence

Pcie, ucie, and ethernet controller experience
Soc implementation with end customers
Interpretation of standard specifications
The role involves leading R&D development projects and key customer engagements within the Design IP Group

Job Summary

  • The role involves leading R&D development projects and key customer engagements within the Design IP Group.
  • Candidates must possess deep expertise in PCIe, UCIe, and Ethernet standards to drive controller IP product delivery.
  • The position requires managing multiple priorities, defining scope with R&D and marketing, and ensuring flawless execution in a matrix organization.

Matching Summary

The role involves leading R&D development projects and key customer engagements within the Design IP Group.

Skills & Requirements

Must-have

  • PCIe, UCIe, and Ethernet controller experience
  • SoC implementation with end customers
  • Interpretation of standard specifications
  • Project lifecycle management from inception to delivery
  • Matrix organizational structure coordination

Nice-to-have

  • Entrepreneurial mindset with ownership attitude
  • Verilog/RTL coding and verification skills
  • Mixed-signal IP design flow familiarity
  • Strong communication with technical and non-technical teams
  • Creative strategic problem-solving abilities

Key Requirements

  • Bachelor's degree in engineering
  • 15+ years of total experience
  • 2+ years of Program Management or Technical Product Management experience
  • Physical Layer and Protocol layer experience on high speed SERDES
  • Experience with PCIe/UCIe LTSSM states and interfaces

Work Rights

Not specified

Tailored Resume

Cover Letter