The Principal HW DFT Engineer will lead the architecture and implementation of advanced DFT strategies for automotive-grade in-vehicle networking devices
Job Summary
The Principal HW DFT Engineer will lead the architecture and implementation of advanced DFT strategies for automotive-grade in-vehicle networking devices.
The role involves close collaboration with RTL and physical design teams to ensure timing closure and immediate test pattern operability upon silicon arrival.
The engineer will drive post-silicon validation and debug activities to improve manufacturing test efficiency and overall test coverage.
Matching Summary
The Principal HW DFT Engineer will lead the architecture and implementation of advanced DFT strategies for automotive-grade in-vehicle networking devices.
Skills & Requirements
Must-have
SoC DFT implementation and verification
Scan insertion and ATPG pattern generation
Post-silicon validation and debug
Static timing closure and constraints
Mentor Graphics Tessent and Synopsys tools
Verilog or SystemVerilog HDL proficiency
Nice-to-have
Collaboration with RTL and physical design teams
Scripting in Tcl, Python, or Perl
Test compression techniques
Gate-level simulation and verification
Key Requirements
B.S./M.S. in Electrical or Computer Engineering
10+ years industry experience in SoC DFT
Experience with static timing closure and silicon bring-up
Proficiency with Mentor Graphics/Siemens Tessent, Cadence, or Synopsys EDA tools