$127,400 - $184,400 usd; not specified; not specif...
Ml/ai timing and power flow
Upf-based methodologies
Fpga solutions
We are seeking a highly skilled ML/AI Timing and Power Flow Expert with deep expertise in flow development, timing, power, library generation, and UPF-based methodologies
Job Summary
We are seeking a highly skilled ML/AI Timing and Power Flow Expert with deep expertise in flow development, timing, power, library generation, and UPF-based methodologies.
In this role, you will architect and optimize advanced ASIC/FPGA implementation flows, focusing on timing and power convergence across full-chip and block-level designs.
This is a highly visible, cross-functional position working closely with design, physical design, CAD, library, and reliability teams to enable best-in-class silicon performance and power efficiency.
Matching Summary
We are seeking a highly skilled ML/AI Timing and Power Flow Expert with deep expertise in flow development, timing, power, library generation, and UPF-based methodologies.
Salary
$127,400 - $184,400 USD; Not specified; Not specified
Skills & Requirements
Must-have
ML/AI timing and power flow
UPF-based methodologies
FPGA solutions
silicon design, verification, implementation
timing and power convergence
scalable, automated flow infrastructure
Nice-to-have
technical excellence, collaboration, innovation
data-driven techniques
anomaly detection, trend identification
Key Requirements
8+ years of industry experience in ASIC/FPGA timing/power/library flow development
6+ years of experience in timing and power flow development
6+ years of experience with STA, power analysis, library characterization tools
6+ years of experience with Tcl, Python, Perl coding
6+ years of experience with timing concepts and methodologies
6+ years of experience in power analysis and optimization
6+ years of hands-on experience with library generation and characterization