Sr Principal Product Engineer – Memory Ip

Cadence

San Jose, California, USA
Base: $154,000 to $286,000; bonus/equity: incentiv...
Onsite
Post-silicon bring-up and debug
Memory ip subsystem integration
Lab equipment for debugging
This role is critical in ensuring successful integration of Memory PHY and Controller IP into customer systems

Job Summary

  • This role is critical in ensuring successful integration of Memory PHY and Controller IP into customer systems.
  • Leverage AI-powered tools and assistants to enhance productivity, improve decision making, and maintain high-quality customer deliverables.
  • Work on cutting-edge memory technologies impacting next-generation systems and collaborate with global teams and industry-leading customers.

Matching Summary

This role is critical in ensuring successful integration of Memory PHY and Controller IP into customer systems.

Salary

Base: $154,000 to $286,000; Bonus/Equity: Incentive compensation (bonus, equity); Benefits: Paid vacation, 401(k) with match, ESPP, medical, dental, vision

Skills & Requirements

Must-have

  • Post-silicon bring-up and debug
  • Memory IP subsystem integration
  • Lab equipment for debugging
  • Schematic reading for SI/PI reviews
  • Customer SOC and system integration
  • High-performance IP development

Nice-to-have

  • AI-powered tools and analytics
  • Customer success and collaboration
  • Innovation and technical leadership
  • Global team collaboration

Key Requirements

  • M.S. with 7+ years or Ph.D. with 5+ years experience
  • Experience with DDR5/4/3, LPDDR5/4/3, HBM3/4, GDDR6/7
  • Strong post-silicon bring-up and debug background

Work Rights

Not specified

Tailored Resume

Cover Letter