$183,800.00 - $263,600.00; not specified; medical,...
Design-for-test (dft)
Scan insertion and bist architectures
Atpg and eda tools
You will be in the Silicon One development organization as an ASIC Implementation Technical Lead with a primary focus on Design-for-Test
Job Summary
You will be in the Silicon One development organization as an ASIC Implementation Technical Lead with a primary focus on Design-for-Test.
You will help lead to drive the DFT and quality process through the entire Implementation flow and post silicon validation phases with additional exposure to physical design signoff activities.
At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond.
Matching Summary
You will be in the Silicon One development organization as an ASIC Implementation Technical Lead with a primary focus on Design-for-Test.
Salary
$183,800.00 - $263,600.00; Not specified; Medical, dental, vision insurance, 401(k) with match, paid parental leave, disability, life insurance, stock units, paid time off
Skills & Requirements
Must-have
Design-for-Test (DFT)
Scan insertion and BIST architectures
ATPG and EDA tools
Gate level simulation
Post-silicon validation and debug
Tcl, Python/Perl scripting
Nice-to-have
Crafting groundbreaking next generation networking chips
Physical design signoff activities
Collaboration and empathy
Key Requirements
Bachelor's or Master's Degree in Electrical or Computer Engineering
10+ years of experience
Prior experience with Jtag protocols (p1500, p1687)
Prior experience with memory BIST and boundary scan
Prior experience with TestMax, Tetramax, Tessent tool sets
Prior experience with test static timing analysis constraints development and timing closure
Ability to work with ATE engineers on pattern translation and validation