Soc Design Verification Engineer

Altera Digital Health

Austin, Texas, United States
$128.9k - $205.9k usd; not specified; not specifie...
Functional logic verification
Systemverilog and uvm
Define and develop verification plans
Perform functional logic verification of an integrated SoC to ensure design will meet specifications

Job Summary

  • Perform functional logic verification of an integrated SoC to ensure design will meet specifications.
  • Replicate, root causes, and debugs issues in the pre-silicon environment.
  • Incorporate and execute security activities within test plans, including regression and debug tests, to ensure security coverage.

Matching Summary

Perform functional logic verification of an integrated SoC to ensure design will meet specifications.

Salary

$128.9k - $205.9k USD; Not specified; Not specified

Skills & Requirements

Must-have

  • functional logic verification
  • SystemVerilog and UVM
  • define and develop verification plans
  • execute verification plans
  • root causes and debugs issues
  • security activities within test plans

Nice-to-have

  • AI techniques in design
  • Design for Debug verification
  • Object oriented programming
  • Scripting in Python, Perl and Tcl

Key Requirements

  • 7+ years of work experience
  • Bachelor’s degree in electrical engineering, computer engineering, computer science
  • unit or block ownership in full hardware design life cycle

Work Rights

Not specified

Tailored Resume

Cover Letter