Lead Application Engineer - Emulation

Cadence

Bs-ee/ce degree with 3-7 years experience
Proficiency in verilog systemverilog vhdl
Strong knowledge of design debug techniques
This role involves working closely with the Sales team to identify and scope opportunities for Cadence SoC Verification solutions

Job Summary

  • This role involves working closely with the Sales team to identify and scope opportunities for Cadence SoC Verification solutions.
  • The successful candidate will plan, execute, and manage key technical evaluations and benchmarks with existing and potential customers.
  • Responsibilities include conducting basic and advanced trainings, presentations, and demos while providing expert technical support to address client queries.

Matching Summary

This role involves working closely with the Sales team to identify and scope opportunities for Cadence SoC Verification solutions.

Skills & Requirements

Must-have

  • BS-EE/CE degree with 3-7 years experience
  • Proficiency in Verilog SystemVerilog VHDL
  • Strong knowledge of design debug techniques
  • Unix/Linux scripting languages ksh bash perl
  • Experience with complex digital design verification

Nice-to-have

  • Cadence Palladium emulation product experience
  • UVM verification methodology experience
  • Low power UPF flow knowledge
  • Excellent communication skills for technical demos
  • Ability to create test cases quickly

Key Requirements

  • Bachelor of Science in Electrical Engineering or Computer Engineering
  • Master's degree preferred
  • 3-7 years of relevant industry experience
  • Proficiency in HDL languages and Unix scripting

Work Rights

Not specified

Tailored Resume

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