The Digital Mixed Signal (DMS) Verification Team is seeking a motivated Design Verification Engineer to support the Industrial Power Group
Job Summary
The Digital Mixed Signal (DMS) Verification Team is seeking a motivated Design Verification Engineer to support the Industrial Power Group.
Responsibilities include verification of state machines and controlling logic, development of directed and constrained random test cases, and implementation of metric-driven verification environments.
The role involves verifying integrated circuits and supporting assigned products through the full product life cycle, with emphasis on verification and potential design assignments.
Matching Summary
The Digital Mixed Signal (DMS) Verification Team is seeking a motivated Design Verification Engineer to support the Industrial Power Group.
Skills & Requirements
Must-have
SystemVerilog
UVM verification environments
Mixed Signal Simulation
Analog blocks modeling
scripting language experience
Nice-to-have
System Verilog Assertion
Formal Verification
custom digital interfaces
linear regulators
switching regulators
Key Requirements
Bachelor’s Degree in Electrical or Computer Engineering
Analog Microelectronics and Digital Systems Design
Strong written and verbal communication skills
Strong general coding, object-oriented programming